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Commit 39afaebc authored by Dominik Zobel's avatar Dominik Zobel
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Highlight difference of serial and parallel memory requests

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1 merge request!74Memory hierarchies lecture
......@@ -266,6 +266,13 @@ One layer of RAM cache between the CPU and the disk.
- Parallel and serial requests possible
:::{.smaller}
\begin{align}
T_{avg,p} &= H_M T_M + (1-H_M) \cdot \color{blue}{T_D}\\
T_{avg,s} &= H_M T_M + (1-H_M) \cdot \color{blue}{(T_M + T_D)}
\end{align}
:::
## Second model version
......@@ -297,8 +304,8 @@ Three layers of caches
:::{.smaller}
\begin{align}
T_{avg,p} &= H_1 T_1 + ((1-H_1)\cdot H_2)\cdot T_2\\
&+ ((1-H_1)\cdot(1-H_2))\cdot T_3
T_{avg,p} &= H_1 T_1 + ((1-H_1)\cdot H_2)\cdot \color{blue}{T_2}\\
&+ ((1-H_1)\cdot(1-H_2))\cdot \color{blue}{T_3}
\end{align}
:::
......@@ -306,8 +313,8 @@ T_{avg,p} &= H_1 T_1 + ((1-H_1)\cdot H_2)\cdot T_2\\
:::{.smaller}
\begin{align}
T_{avg,s} &= H_1 T_1 + ((1-H_1)\cdot H_2)\cdot(T_1+T_2)\\
&+ ((1-H_1)\cdot(1-H_2))\cdot(T_1+T_2+T_3)
T_{avg,s} &= H_1 T_1 + ((1-H_1)\cdot H_2)\cdot \color{blue}{(T_1+T_2)}\\
&+ ((1-H_1)\cdot(1-H_2))\cdot \color{blue}{(T_1+T_2+T_3)}
\end{align}
:::
......
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